A semiconductor device may comprise a gate structure having a multiplicity of gates, or memory cell gates, which are used to electronically store data. A word line (WL) typically is disposed along the tops of many—perhaps hundreds or even thousands—of these memory cell gates. FIG. 1 represents a cross-sectional view of a gate structure showing a plurality of gates or memory cell gates. The gate structure 1 of FIG. 1 has a plurality of gates 10 disposed on a substrate 20 and defined by a space 30. The plurality of gates 10 may comprise a tunnel oxide layer 50, a floating gate 60, an oxide/nitride/oxide (ONO) laminate layer 70, and a control gate 80. The WL (not shown) would eventually be formed above the finished structure.
Differences in gate space geometries and variability in WL space sizes can lead to vastly different charge buildup in the isolation oxide resulting in unexpected responses of the semiconductor gate response in operation. Indeed these differences may be based upon a needed design of the semiconductor.
“WL capacitance” refers to the capacitance between the word line and adjacent control gates. When the separation between two adjacent control gates is reduced, the structure is deemed to be a “dense WL” and the risk of interference between the WL capacitances for the control gates increases. For example, gates between the spaces 40 of FIG. 1 indicate a dense WL region 100 or a region where there is an increased risk of WL interference.
The remains a need in the art for an improved gate structure that reduces the risk of interference between word line particularly in dense WL structures. There remains a need in the art for an improved system, process or method for fabricating a semiconductor having a plurality of airgaps.
Salicide, or a self-aligned silicide, layer may be applied in the formation of a semiconductor device or gate structure to reduce resistance and provide good ohmic contacts. For example, a cobalt containing silicide applied to a transistor or gate that has been isolated from other gates using WL spaces may serve to reduce the resistance of the gate electrode. However, application of a cobalt containing silicide layer to a semiconductor device itself may not be sufficient to reduce interference especially gate structures having dense WL structures. There remains a need in the art for improved gate structures and methods of fabricating such structures to reduce the extent of interference, in particular, in gates structures having dense WL regions.